A LIttle Words

About Me

Hello! I hope you have a good day. I am Sevval YILDIZ, and I am an engineer from Istanbul, Turkey, with a strong desire for learning and self-improvement. The detailed information about me can be found in this page.

In terms of my educational background, I am currently pursuing a Master’s degree in Computer Engineering, Computer Science and Multimedia, at the University of Pavia. I also hold a Bachelor’s degree in Electronics and Communication Engineering from Istanbul Technical University. During my academic journey, I have had the privilege of gaining practical experience through internships and research positions. Outside of my academic and professional pursuits, I was a proud member of the Istanbul Technical University Women’s Basketball Team. I have learned the value of teamwork, discipline, and perseverance. About me, I believe in the power of collaboration and strive to contribute positively to any team I am a part of. Also I like taking photos and drawing. My native language is Turkish, and I have a strong command of English. This proficiency allows me to effectively communicate in a professional environment.

about me- graduation photo

Experiences

DIGITAL DESIGN ENGINEER/RESEARCHER

Scientific and Technological Research Council of Turkey
October 2020 – September 2022
 

Design and testing of FPGA codes. During this process, I focused on various projects ranging from small interfaces to large and purpose-specific designs. I primarily utilized VHDL for design purposes using Vivado and conducted simulation work using ModelSim.

DIGITAL DESIGN and VERIFICATION INTERN

Yongatek Microelectronics R&D Inc.
June 2020 – August 2022
 

Design and verification of a gray scale histogram equation using VHDL. I designed this system on an FPGA that performs histogram equalization, an image enhancement technique, by manipulating the histogram curve of an image while optimizing the area utilization and processing speed.

DIGITAL DESIGN INTERN/SUMMER INTERN

Istanbul Technical University VLSI Labs
June 2019 – August 2019
 

A finite state machine design was implemented to control an intelligent traffic light system using two different methods. The designed systems were realized in Verilog and tested on circuits.

Technical Skills

  •  Javascript

  • HTML

  • CSS

  • Visual Studio Code

  •  Python

  • Assembly

  • MATLAB

  • VHDL

  • Verilog

  • LTSpice

  • Cadence

  • Modelsim

  • Vivado

  • MS Office

  • Wireshark

Languages

  • English – C1 Level (IELTS)

  • Turkish – Native

  • Italian – Beginner

Topics of Interest

  • Digital electronic design 

  • Machine learning

  • Web development

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